A walkthrough of the custom Mrav CPU core describes using cocotb and Python scripts to control RTL simulation and a Python class to model RAM, without a Verilog testbench.
The material presents tests for a custom CPU core, Mrav, using cocotb and Python scripts to control RTL simulation. It also describes a Python class for modeling RAM.
To try a similar approach, first identify the signals and operations that the core needs to exercise. Organize test cases in Python, then use cocotb to drive the simulation and check expected results.
Model RAM in a Python class, following the described approach, and connect that model to the simulation flow. Compare observed values with expected ones and add cases for operations relevant to your project.
The account notes that this allows CPU testing without writing Verilog testbenches or a RAM controller. It does not specify commands or performance results; adapt the flow to your RTL environment. If you use AI to study or apply the material, do not submit confidential code, credentials, or personal data without authorization.