Published on July 9, 2026, the project describes a two-core GPU on a US$30 FPGA, with a 16-bit ISA, assembler, J++ language, compiler, and AI inference at 81 MHz.
Published on July 9, 2026, the project presents a two-core GPU implemented on a US$30 FPGA. It includes a 16-bit ISA and assembler, a J++ language and compiler, as well as branch divergence and warp scheduling. The report says the hardware runs AI model inference at 81 MHz.
The project offers a concrete example of a GPU architecture implemented in hardware. To check the details, consult the original project materials and compare the descriptions of the ISA, compiler, and scheduling with the design and reported results. The brief account does not provide other benchmarks or test conditions.