Radar ·
Qwenputer: RISC-V CPU described in the weights of Qwen3.5-4B (unverified)
An author describes a Qwen3.5-4B model that, he says, runs C and MicroPython code using Gated DeltaNet layers as memory. The benchmark claims have not been verified.
According to the publication dated 28 October 2026 collected in Radar, an author presents Qwenputer, a Qwen3.5-4B model that, he says, contains a RISC-V CPU encoded in its weights. According to the description, the Gated DeltaNet layers would act as RAM and allow C and MicroPython programs to run during forward passes. The material shows the use of the Gated DeltaNet state as general-purpose memory.
The author's performance claims have not been verified, and the source offers no independent evidence. To consult the original, find the publication by its title and stated date, compare the description with the artifacts and evaluations the author has released, and confirm any result before citing it. If you use AI to study this topic, do not paste personal data, CPF numbers, e-mail addresses or credentials into prompts; replace them with placeholders before sending.
Original source: Qwenputer: CPU RISC-V embutida nos pesos do Qwen3.5-4B